Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme

In this paper, a high-efficient lined-based architecture for the 9/7 discrete wavelet transform (DWT) based on lifting scheme is proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The critical path of the proposed architecture is reduced. Filter coefficients of the biorthogonal 9/7 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using less shifts and additions. The proposed architecture is 100% hardware utilization and ultra low-power. The architecture has regular structure, simple control flow, high throughput and high scalability. Thus, it is very suitable for newgeneration image compression systems, such as JPEG-2000. Key-Words: 9/7 discrete wavelet transform (DWT), horizontal filter (HF), vertical filter (VF), linedbased architecture, lifting scheme, JPEG-2000.